DESIGN FLOWS

The flowchart (Arthur H.M et al) exists the loops; the criteria behind is that the algorithm of physical design steps invites the approximated accuracy and or solution yet the system if idealized the layout system can not find a perfect satisfaction. Analyse progression, powerful tools and teamworks are called to collaborate the elaboration till the specifications and simulations met.

TOP DOWN FLOW


Speaking of custom mixed signal Integrated Circuit (IC) design of a chip, the top down flow resembles the above figure of a design flow in general (not at detailed details for mixed signal design flow).

High level input shall model in VHDL, VERILOG, or SYSTEM VERILOG High Descriptive Language (HDL), privilleged Electrical System Language (ESL), for design modeling and architecture; then producing the netlists for uses in the next steps of the design flow.

Schematic represents the diagram connectivities of the designed symbols indicated the components resolved from the digital cell library and or analog cell library.

HDL modeling can be dumped into the Simualtion tool to debug and check clock synch. In custom design tool, schematic designs are simulated at logics, circuits of mixed level for their component types.

Synthetic design uses the digital cell library so that the simulated HDL modeling architectures, after reading files of designs into the tool, shall give the netlist of gate level descriptions and symbols.

For digital designs or Very Large Scale Integrity (VLSI) designs the synthethic database files (contained of gate level netlists) can be read into the design and physical compiler that developed for uses of sea of gates and or standard cell library to run and output the placement of the design.

Placement is the process of placing the gates into the distributed channels whereas the optimization of the connectivities shall be met because of their relative closeness of the sub blocks placed that predict or re-iterate until meeting the area and timing constraints.

Placement can be automatic (as uses of the standard cell library), custom (as uses of analog cell library), semi-custom (as uses partial degital and partial analog simultaneously), and or following the instructions stated in the schematic approved.

Routing is the Electronic Design Automation (EDA) tool or module (within the complex suites of tool) developed for a virtual running the polygonal wires connecting correctly the digital instances together, the analog instances together, and the digital-analog instances together as the schematic description of connectivities. It is very critical to follow the orders of design engineers regarding the critical paths.

Routing tool can be automatic and manual and or semi custom that ensure the area and timing constraints.

The custom layout part, on the other side, as the physical design layout part, after passing the design rule and connectivities rule checks, will be extracted. The extraction process does to give information annotated netlist including all parasitic elements; on the extracted layout cells or in the scripting reports, which are not or only partially accounted for in the circuit netlist (schematic). This annotated netlist shall be compared to the front-end netlist (or the original netlist generated after the schematic and or the synthetic design stages) to get a report of the discrepancies surprisingly introduced parting from the allowed parasictics.

Resimulation takes place to reach the finished netlist after clocks synthetic and buffering that created delays due to large fan-outs; the needs call to resimulate the compiled netlists. The post iterations in development of system on chip to some points shall end the story when the finished netlist consensus.

What is Simulation? The singly word is found in SPICE (Simulation Program with Integrated Circuit Emphasis), the circuit simulator; this engine is developed by Larry Nagel and others in UC of Berkeley released in 1972 (Art the Analog - Alan Hasting).

Before sysnthesis, the logic simulation takes place to give nominal delay value; after the synthesis, timing simulation take place to result the fanout-based delay estimation, yet not the wire delay considered until post simulation that serve the finished netlist.

BOTTOM UP DESIGN

This often means to start design at the specification of the transistor level; its verification and simulation shall consume time, effort, and cost. The team works generate the complex communication. In the ending, putting together the architecture of a developed system on chip plausibly create more adjustments and simulation.

This old traditional fashion of design have practiced long time ago; it has been good to develop the transistor cells, macro cells, sub-blocks, and instances or the pdk in the Intellectual Properties (IPs) libraries for the common uses.

ANALOG IC (AIC) DESIGN FLOW

Except fabrication, the front-end and back-end designers respond for all of the steps of the design process.

Firstly definition and synthesis of the function determine the capability and performance of the design.

Designers shall be able to confirm the designs for fabricated. Being able to speak that idea plausible for implementation approve the designs; thenfore, it resemble the design flow in general descripting in the beginning of this piece writing. Except, using the Verilog to model the high level of input, analog flow uses a-verilog (property of Cadence) and or a-vhdl, and or the schematic drawing resolve from the symbolic components library.

The following summary describe in words about AIC design process:

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REFERENCES

Mixed Signal Layout Generation Concepts by Arthur HM et als
Mask Design Principle book by C&J Saints
The Art of Analog Layout by Alan Hastings
Automatic Layout Modification by Michael Reinhardt

CMOS AC Design by Phillip Allen et al