CMOS TECHNOLOGY

Traditionally, catergories of silicon technology, thousands of words illustrate in the following famed picture :)

BASIC MOS SEMICONDUCTOR FABRICATION PROCESSES

Semiconductor technology goes in the process, ways to fabricate semiconductor components. Description of the steps include oxidation, diffusion, ion implantation, deposition, and etching. Way to define the area of the semiconductor subjected to processing called photolithography.

OXIDATION

Oxidation means oxide growth, the process by which the layer of silicon dioxide (SiO2) is formed to the surface of the silicon wafer.

DIFFUSION

The movemet of impurity atoms of the surface of the material into the bulk of the material. The reaction take place in consumption of impurities and under high temperature environment. Two types in basic diffusion mechanism; one type assumes the infinite source of impurity of the surface during time the impurity allowed to diffuse. Other type assumes the finite source of impurity at the surface at time initially. This requires the surface be free of silicon dioxide or silicon nitride layers

ION IMPLANTATION (II)

Widely used in MOS components; II is a process, by which particular dopant (impurity) accelerate in an electric field to a high velocity and physically lodge within the semiconductor material. This cause the collision of the lattice atoms, avoiding the undesirable channeling of ions deep into silicon. This process can be used in diffusion to insert the impurities into the semiconductor material. II has many advantages over the thermal diffusion; such as accurate control doping; at room temperature, and possibility of implantation through a thin layer, allowing control over the implanted impurities.

DEPOSITION

The films of various materials are deposited on the silicon wafer. These films may be deposited used techniques of deposition by evaporation (1), sputtering (2), Chemical Vapor Deposition (CVD) (3). CVD done at the high pressures can be done at the low pressures called LPCVD where diffusivity increases significantly.

ETCHING

The process removes the exposed (unprotected) material. A protected layers, called a mask, cover the film except the area etched. Two important properties notice; selectivity and anisotropy; selectivity etches only the areas desired layer to be etched. Anitropy is property of etching to manifest itself in one direction e.g. a perfect etchant will etch in one direction only.

PHOTOLITHOGRAPHY

The word implies printing with light. The complete process transfers an image from a photomask or computer database to a wafer. It basic components are photoresist material and the photomask used to expose some areas of the photorist to ultraviolet (UV) light while shielding the remainder. Each layer of the device components of IC is physically defined a collection of geometries. CAD tool draws the layer and generate the electronic data format. The developing process expose and remove the photoresit; the process repeats. Basic steps of photolithography are (1) expose (2) develop (3) etch (4) remove photoresist. Printing is the process to expose the selective areas of wafer to light thru a photmask, includes three types (1) Contact printing (2) Proximity printing (3) Projection printing.

N-WELL CMOS FABRICATION STEPS

(1) To grow a thin silicon dioxide region on a p- substrate wafer (2) To deposit a photoresist material on top of the oxide make the region for N-WELL. (3) n-type impurity is implanted into the wafer (4) Photoresist removes (5) high temperature oxidation/drive-in take place causing the implanted ion diffused into the p-substrate (6) Oxide removal and subsequent growth of a thin pad oxide layer (pad oxide is to protect the substrate from stress for difference in the thermal expansion of silicon and silicon nitride) (7) Layer of silicon nitride is deposited over the entire wafer (8) Photoresist deposits, patterns, develops; then silicon nitride remove from the areas patterned (9) silicon nitride and photoresist remain in areas active devices will reside. These regions silicon nitride remained call active area or moat. (10) Global n-type field (channel stop) implant (11) Photorist is removed, redeposited, and patterned using p-type field (channel top) implant mask followed by a p-field implant (12) Thick silicon dioxide layer is grown over the entire wafer where SiN2 exists (SiN2 impede oxide grown) (13) The remained SiN2 is removed; thin oxide be the gate oxide grown followed by a polysilicon deposition (14) Polysilicon then patterned and etched to make a transistor gate (15) The lightly doped drain/source (LDD) process structure deposits a spacer oxide over the patterned polysilicon followed by anisotropic oxide etch leaving spacer on each side of the gate polysilicon (16) Photoresist is applied and patterned where n-channel transistors required to make n+ source and drain; n+ are made for metal connection to n-material such as the n-well (17) a lighter n- implant to align the S/D regions with Poly gate; the spacer is etched (18) These steps repeat for p-channel transistors (19) Annealing activates the implanted ions (20) n- and p- channel LDD transistors are complete except terminal connections. (21) Contact preparation step (22) A Passivation layer cover entire wafer to protect from chemical intrusion or scratching. In sum, scaling illustrates the relative dimensions. Silicide technology needed reduces interconnect resisticity. Salicide technology (self aligned silicide) provide low resistance S/D connection awa low resistance plysilicon. MOM capaciors will be discussed in one piece of writing.

THE P-N JUNCTION (PNJ)

The p-n junction forms the diodes that are noticed in seminconductor devices. The concept of PNJ relates with the depletion region width, capacitance, reverse bias or breakdown voltage, and diode equation. Let talk about the diodes.

DIODES

A semiconductor device allows current to flow in one direction. Its architecture resembles the formation of the p-type and n-type diffusion physically touched. Two general types include; Intentional Architecture that functions as the Electro-Static-Discharge (ESD) to protect the device from explossion; Parasitic Formation that occurs unwanted when p-type and n-type material touched. In CMOS; diode operates as a norm a reverse biased that prevents electrical currents from flowing between opposite polarity diffusions when abutting, but the forward biased diode allows the currents flow without restriction. Parts of Diode include Anode (p-type diffusion) and Cathode (n-type diffusion). Knowing the properties of diode makes uses the joy designs.

N-Well CMOS Inverter forms in connection of NMOS and PMOS. Five parasitic diodes found in an inverter of a CMOS technology include each at the touches of S/D n+ channels in NMOS, S/D p+ channels in PMOS, and abutment of N-Well and p-substrate wafer.

THE MOS (METAL OXIDE SEMICONDUCTOR) TRANSISTOR

The structure, of n-channel and p-channel MOS transistor used n-well technology, includes the p-channel device that is characterized with two heavy doped p+ region diffusion into a lightly doped n- material called the well, and the n-channel transistor that is formed by two heavily doped n+ regions within a lightly doped p-sustrate; they have a gate on the surface between Source and Drain.

THE PASSIVE COMPONENTS

CAPACITORS

MOS Capacitor: Formation is to connect source to drain Terminals of a MOS transistor; called a single process. TOtal load of capacitance on the output of a MOS gate includes Gate Capacitance (Cg), Diffusion Capacitance (CB), Routing Capacitance (Cm).

A good capacitor required when design Analog IC (AIC) for they are used in amplifier designs, gain determining components in charge amplifier, bandwidth-determining components in gm/C filters, charge storage devices in switched-capacitor filters and Digital-to-Analog Converters (DAC), and other places as well ... Characteristics wanted in these devices include; good matching accuracy, low voltage co-efficient, high ratio of desired capacitance to parasitic capacitance, high capacitance per unit area, and low temperature dependence.

RESISTORS

Resistance is determined by the doping level of the region and the dimension of the resistor. Calculation of resistance deploys the Ohm's Law, that says Resistance (R) equals the Voltage (V) divided by Current (I); Resistance is also calculated by multiply the ratio of Length/Width of the block of material to the Sheet Raw of the material; this creates the phenomenon that one square block has the same resistance value as four square blocks edges-to-edges. Known Process parameters help estimate the resistor value. The sheet resistance for conductor shall be already measured and listed in the job manuals.

Digital-to-analog conversion uses the resistor. Resistors in AIC include diffusion (found at Source/Drain), polysilicon (gate), n-well or p-well resistors (wells contacted with the S/D diffusion); metal is also used as resistor.

OTHER CONSIDERATIONS OF CMOS TECHNOLOGY

The limitation of CMOS technology include latch-up, temperature, and noise; these shall be discussed later. The other components include the Bipolar Junction Transistor (BJT), and or Bipolar combined with CMOS called BiCMOS. BJT has three terminals (Emitter (E), Collector (C), Base (B)) differed from NMOS that has four terminals (In, Source, Drain, Out).

INTEGRATED CIRCUIT LAYOUT

Understanding the circuits beyond the schematic designs shall be unique and required for the designs shall be possibly speaking in terms of physical designs. Physical designs refer to Layout.

IC Designers consider the processes of designing a circuit implying toward the physical layout that can operate. Moreover, the layout techniques considered are described below:

MATCHING CONCEPTS

Two components electrically equivalent are drawn as identical units -- called unit matching principle; the identification include the bodies of devices and the connectivities and surrounding area, space, and all. In analogy, two devices are mirrored to the line of reflection. Truly, two physical devices identical in physical material and physical shapes through a line of reflection. The matching concept applies toward, MOS devices such as NMOS, PMOS, Capacitor layouts, Resistor layouts. Layouts follow the design rules for layouts and layout rules.

LAYOUT RULES

Layout Rules are reseached and developed by the Foundries that set out the guidelines for the layout designer to follow the sets of rules for the varies of CMOS Technologies to ensure that the IC Designs are manufacturable and fabricated into chips for consumers. Basic rules covers the required width, space and surrounding dimensions, L-shapes and U-shapes and abutting width and space, and more....

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IC Designers take in all the knowledge of the CMOS Technologies, EDA tools, Design Rules, Layout Techniques, and required disciplinaries to produce the developed system on chip that the customers happily spend money for.

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DESIGN FLOWS

The flowchart (Arthur H.M et al) exists the loops; the criteria behind is that the algorithm of physical design steps invites the approximated accuracy and or solution yet the system if idealized the layout system can not find a perfect satisfaction. Analyse progression, powerful tools and teamworks are called to collaborate the elaboration till the specifications and simulations met.

TOP DOWN FLOW


Speaking of custom mixed signal Integrated Circuit (IC) design of a chip, the top down flow resembles the above figure of a design flow in general (not at detailed details for mixed signal design flow).

High level input shall model in VHDL, VERILOG, or SYSTEM VERILOG High Descriptive Language (HDL), privilleged Electrical System Language (ESL), for design modeling and architecture; then producing the netlists for uses in the next steps of the design flow.

Schematic represents the diagram connectivities of the designed symbols indicated the components resolved from the digital cell library and or analog cell library.

HDL modeling can be dumped into the Simualtion tool to debug and check clock synch. In custom design tool, schematic designs are simulated at logics, circuits of mixed level for their component types.

Synthetic design uses the digital cell library so that the simulated HDL modeling architectures, after reading files of designs into the tool, shall give the netlist of gate level descriptions and symbols.

For digital designs or Very Large Scale Integrity (VLSI) designs the synthethic database files (contained of gate level netlists) can be read into the design and physical compiler that developed for uses of sea of gates and or standard cell library to run and output the placement of the design.

Placement is the process of placing the gates into the distributed channels whereas the optimization of the connectivities shall be met because of their relative closeness of the sub blocks placed that predict or re-iterate until meeting the area and timing constraints.

Placement can be automatic (as uses of the standard cell library), custom (as uses of analog cell library), semi-custom (as uses partial degital and partial analog simultaneously), and or following the instructions stated in the schematic approved.

Routing is the Electronic Design Automation (EDA) tool or module (within the complex suites of tool) developed for a virtual running the polygonal wires connecting correctly the digital instances together, the analog instances together, and the digital-analog instances together as the schematic description of connectivities. It is very critical to follow the orders of design engineers regarding the critical paths.

Routing tool can be automatic and manual and or semi custom that ensure the area and timing constraints.

The custom layout part, on the other side, as the physical design layout part, after passing the design rule and connectivities rule checks, will be extracted. The extraction process does to give information annotated netlist including all parasitic elements; on the extracted layout cells or in the scripting reports, which are not or only partially accounted for in the circuit netlist (schematic). This annotated netlist shall be compared to the front-end netlist (or the original netlist generated after the schematic and or the synthetic design stages) to get a report of the discrepancies surprisingly introduced parting from the allowed parasictics.

Resimulation takes place to reach the finished netlist after clocks synthetic and buffering that created delays due to large fan-outs; the needs call to resimulate the compiled netlists. The post iterations in development of system on chip to some points shall end the story when the finished netlist consensus.

What is Simulation? The singly word is found in SPICE (Simulation Program with Integrated Circuit Emphasis), the circuit simulator; this engine is developed by Larry Nagel and others in UC of Berkeley released in 1972 (Art the Analog - Alan Hasting).

Before sysnthesis, the logic simulation takes place to give nominal delay value; after the synthesis, timing simulation take place to result the fanout-based delay estimation, yet not the wire delay considered until post simulation that serve the finished netlist.

BOTTOM UP DESIGN

This often means to start design at the specification of the transistor level; its verification and simulation shall consume time, effort, and cost. The team works generate the complex communication. In the ending, putting together the architecture of a developed system on chip plausibly create more adjustments and simulation.

This old traditional fashion of design have practiced long time ago; it has been good to develop the transistor cells, macro cells, sub-blocks, and instances or the pdk in the Intellectual Properties (IPs) libraries for the common uses.

ANALOG IC (AIC) DESIGN FLOW

Except fabrication, the front-end and back-end designers respond for all of the steps of the design process.

Firstly definition and synthesis of the function determine the capability and performance of the design.

Designers shall be able to confirm the designs for fabricated. Being able to speak that idea plausible for implementation approve the designs; thenfore, it resemble the design flow in general descripting in the beginning of this piece writing. Except, using the Verilog to model the high level of input, analog flow uses a-verilog (property of Cadence) and or a-vhdl, and or the schematic drawing resolve from the symbolic components library.

The following summary describe in words about AIC design process:

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REFERENCES

Mixed Signal Layout Generation Concepts by Arthur HM et als
Mask Design Principle book by C&J Saints
The Art of Analog Layout by Alan Hastings
Automatic Layout Modification by Michael Reinhardt

CMOS AC Design by Phillip Allen et al